Along with the blooming development in the electronic industry, electronic products tend to be made compact in size and with high performances, multiple functions and high speed. In order to satisfy the requirements for high integration and miniaturization of semiconductor devices, circuit boards for carrying a plurality of active/passive components and circuits have evolved from double-layer boards to multi-layer boards, such that in the condition of a limited space occupied by the multi-layer circuit board, the useful circuit area of the circuit board can be enlarged using the interlayer connection technology, so as to desirably achieve a high density arrangement of integrated circuits in the multi-layer circuit board.
A conventional multi-layer circuit board is generally fabricated by a laminated method or a build-up method.
FIGS. 1A to 1C show the procedural steps of a conventional laminated method for fabricating a multi-layer circuit board. As shown in FIG. 1A, first, a plurality of circuit boards 11, 12, 13 are prepared each made of copper foils and insulating substrate materials. The circuit board 11 serves as a core circuit board having upper and lower circuit layers 11a, 11b and a plurality of conductive vias 11c. The circuit boards 12, 13 each has a circuit layer 12a, 13a on a side thereof and a conductive metal layer 12c, 13c on another side thereof opposite to the circuit layer 12a, 13a. Next, a prepreg 14 made of fiber or thermosetting resin (such as epoxy resin, phenolic polyester and the like) serves as an adhesive layer to be respectively disposed between the circuit boards 11 and 12 and between the circuit boards 11 and 13. Then, laminating and heat press processes are performed to attach and stack the circuit boards 11, 12, 13 together to form a multi-layer junction board, as shown in FIG. 1B. A drilling process is carried out to form a plurality of through holes in the multi-layer junction board, and a conductive metal layer is plated on inner wall of the through holes to form plated through holes 15. Finally, as shown in FIG. 1C, a patterning process is performed on the outermost conductive metal layers 12c, 13c to fabricate patterned circuit layers 12b, 13b, such that the circuit boards 11, 12, 13 can be electrically interconnected via the plated through holes 15, thereby fabricating a multi-layer circuit board 10 having six circuit layers.
FIGS. 2A to 2E show the procedural steps of a conventional build-up method for fabricating a multi-layer circuit board. As shown in FIG. 2A, a core circuit board 21 is first prepared comprising a resin core layer 211 having a predetermined thickness and circuit layers 212 respectively formed on top and bottom surfaces of the resin core layer 211, wherein a plurality of plated through holes 213 are formed in the resin core layer 211 to electrically interconnect the circuit layers 212 on the top and bottom surfaces of the resin core layer 211. As shown in FIG. 2B, a build-up process is performed to apply an insulating layer 22 respectively on the top and bottom surfaces of the core circuit board 21, and a plurality of blind holes 23 are provided in each insulating layer 22 and reach the corresponding circuit layer 212. As shown in FIG. 2C, a metallic conductive film 24 is coated over each insulating layer 22 and an inner wall of each blind hole 23. Then a resist layer 25 is disposed on each metallic conductive film 24 and is formed with a plurality of openings 250 to expose a predetermined portion of the corresponding metallic conductive film 24 for subsequently forming patterned circuits. As shown in FIG. 2D, an electroplating process is carried out to form a patterned circuit layer 26 and a plurality of conductive blind holes 23a in the openings 250 of each resist layer 25, allowing the circuit layer 26 to be electrically connected to the circuit layer 212 via the conductive blind hole 23a. Then, the resist layer 25 and the portion of the conductive film 24 covered by the resist layer 25 are removed by etching. This thereby forms a build-up structure 20a. Similarly, as shown in FIG. 2E, the above procedural steps can be repeated to form another build-up structure 20b on the build-up structure 20a so as to gradually form more build-up structures and fabricate a multi-layer circuit board 20.
However, by employing either the aforementioned laminated method or build-up method to fabricate a multi-layer circuit board, generally in order to avoid warpage of the circuit board caused by unbalanced forces exerted on the circuit board during the process of stacking the circuit structures, it is necessary to perform simultaneously the stacking process on the top and bottom surfaces of the core circuit board, thereby forming a circuit board having a symmetrical circuit stacking structure.
Furthermore, along with the growth of portable communication, network and computer products, semiconductor packages having a high density and multiple pins, such as Ball Grid Array (BGA), Flip Chip, Chip Size Package (CSP) and Multi Chip Module (MCM) packages, have become the mainstream products on the semiconductor market. Thus, the chip mounting side of the circuit board should be formed with high-density and fine circuits to be suitable for highly integrated semiconductor chips. Correspondingly, another side of the circuit board for being mounted to an external electronic device may not be necessary to have such high circuit density as the chip mounting side thereof. However, since a symmetrical stacking process needs to be adopted to fabricate the conventional circuit stacking structure, that is, the circuit stacking process should be simultaneously perform on the top and bottom surfaces of the core circuit board, the side of the circuit board for being mounted to the external electronic device, not requiring a high circuit density, would also be subject to the same process for stacking multiple circuit layers as the chip mounting side of the circuit board, thereby causing a waste of material and undue consumption of the fabrication processes and cost.